Verilog Modules

chargepump

TerosHDL

Entity: chargepump

  • File: chargepump.v

Diagram

clk resetn [7:0] period chargepump_pin

Description

SPDX-License-Identifier: ISC

Ports

Port name Direction Type Description
clk input
resetn input
period input [7:0]
chargepump_pin output

Signals

Name Type Description
cp_counter reg [7:0]
chargepump reg

Processes

  • unnamed: ( @(posedge clk) )

Type: always







spi

TerosHDL

Entity: SPI

  • File: spi.v

Diagram

clk resetn SCK CS COPI [7:0] tx_byte CIPO [7:0] rx_byte rx_byte_ready

Description

SPDX-License-Identifier: ISC Mode 0 8Bit transfer SPI Peripheral implementation

Ports

Port name Direction Type Description
clk input
resetn input
SCK input
CS input
COPI input
CIPO output
tx_byte input [7:0]
rx_byte output [7:0]
rx_byte_ready output

Signals

Name Type Description
COPIr reg [1:0] Registers to sync IO with FPGA clock
CSr reg [1:0]
rx_byte_ready_r reg Output Byte and ready flag
rxbitcnt reg [2:0] counts up
txbitcnt reg [2:0] counts down
SCK_risingedge wire Assign wires for SPI events, registers assigned in block below
SCK_fallingedge wire
CS_active wire active low
COPI_data wire

Processes

  • unnamed: ( @(posedge clk) )

Type: always

Instantiations

  • sck_rising: rising_edge_detector_tribuf
  • sck_falling: falling_edge_detector_tribuf






microstepper_control

TerosHDL

Entity: microstepper_control

  • File: microstepper_control.v

Diagram

clk resetn [9:0] config_fastdecay_threshold config_invert_highside config_invert_lowside step dir enable_in analog_cmp1 analog_cmp2 wire s1 wire s2 wire s3 wire s4 [7:0] blank_timer0 [7:0] blank_timer1 [9:0] off_timer0 [9:0] off_timer1 [7:0] minimum_on_timer0 [7:0] minimum_on_timer1 phase_a1_l_out phase_a2_l_out phase_b1_l_out phase_b2_l_out phase_a1_h_out phase_a2_h_out phase_b1_h_out phase_b2_h_out faultn offtimer_en0 offtimer_en1 [7:0] phase_ct

Description

SPDX-License-Identifier: ISC

Ports

Port name Direction Type Description
clk input
resetn input
phase_a1_l_out output
phase_a2_l_out output
phase_b1_l_out output
phase_b2_l_out output
phase_a1_h_out output
phase_a2_h_out output
phase_b1_h_out output
phase_b2_h_out output
config_fastdecay_threshold input [9:0]
config_invert_highside input
config_invert_lowside input
step input
dir input
enable_in input
analog_cmp1 input
analog_cmp2 input
faultn output
s1 input wire
s2 input wire
s3 input wire
s4 input wire
offtimer_en0 output
offtimer_en1 output
phase_ct output [7:0]
blank_timer0 input [7:0]
blank_timer1 input [7:0]
off_timer0 input [9:0]
off_timer1 input [9:0]
minimum_on_timer0 input [7:0]
minimum_on_timer1 input [7:0]

Signals

Name Type Description
step_r reg [2:0]
dir_r reg [1:0]
enable reg
step_rising wire
fault0 wire Fault (active low) if off timer starts before minimum on timer expires
fault1 wire
phase_a1_h wire
phase_a1_l wire
phase_a2_h wire
phase_a2_l wire
phase_b1_h wire
phase_b1_l wire
phase_b2_h wire
phase_b2_l wire
phase_a1_l_control wire Low Side - enable
phase_a2_l_control wire
phase_b1_l_control wire
phase_b2_l_control wire
phase_a1_h_control wire High side - enable, and fault shutdown
phase_a2_h_control wire
phase_b1_h_control wire
phase_b2_h_control wire
fastDecay0 wire Fast decay is first x ticks of off time default fast decay = 706
fastDecay1 wire
slowDecay0 wire Slow decay remainder of off time - Active high
slowDecay1 wire

Processes

  • unnamed: ( @(posedge clk) )

Type: always

  • unnamed: ( @(posedge clk) )

Type: always

  • unnamed: ( @(posedge clk) )

Type: always

Description
Fault latches until reset

  • unnamed: ( @(*) )

Type: always







spi_state_machine

TerosHDL

Entity: spi_state_machine

  • File: spi_state_machine.v

Diagram

num_motors num_encoders word_bits dda_bits use_dda move_duration_bits encoder_bits encoder_velocity_bits default_microsteps default_current BUFFER_SIZE default_clock_divisor current_bits reserved_channels resetn wire [word_bits-1:0] word_data_received wire word_received wire [`DUAL_HBRIDGE-1:0] PHASE_A1 wire [`ULTIBRIDGE-1:0] analog_cmp1 wire [`ULTIBRIDGE-1:0] analog_cmp2 wire [num_encoders-1:0] ENC_A wire halt wire [num_motors-1:0] STEPINPUT wire [num_motors-1:0] DIRINPUT wire [num_motors-1:0] ENINPUT wire [num_motors-1:0] STEPOUTPUT CLK pwm_clock wire [`LA_IN:1] LA_IN wire [`LA_OUT:1] LA_OUT [word_bits-1:0] word_send_data wire [`DUAL_HBRIDGE-1:0] PHASE_A2 wire [`DUAL_HBRIDGE-1:0] PHASE_B1 wire [`DUAL_HBRIDGE-1:0] PHASE_B2 wire [`DUAL_HBRIDGE-1:0] VREF_A wire [`DUAL_HBRIDGE-1:0] VREF_B wire CHARGEPUMP wire [`ULTIBRIDGE-1:0] analog_out1 wire [`ULTIBRIDGE-1:0] analog_out2 wire [`ULTIBRIDGE-1:0] PHASE_A1 wire [`ULTIBRIDGE-1:0] PHASE_A2 wire [`ULTIBRIDGE-1:0] PHASE_B1 wire [`ULTIBRIDGE-1:0] PHASE_B2 wire [`ULTIBRIDGE-1:0] PHASE_A1_H wire [`ULTIBRIDGE-1:0] PHASE_A2_H wire [`ULTIBRIDGE-1:0] PHASE_B1_H wire [`ULTIBRIDGE-1:0] PHASE_B2_H wire [num_encoders-1:0] ENC_B wire buffer_dtr wire move_done wire [num_motors-1:0] DIROUTPUT wire [num_motors-1:0] ENOUTPUT

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
num_motors 1
num_encoders 0
word_bits 64
dda_bits 64
use_dda 1
move_duration_bits 32
encoder_bits 32
encoder_velocity_bits 32
default_microsteps 1
default_current 140
BUFFER_SIZE 2
default_clock_divisor 32
current_bits 4
reserved_channels 32 Represents the channel length to reserve, ill advised to change

Ports

Port name Direction Type Description
LA_IN output wire [`LA_IN:1]
LA_OUT output wire [`LA_OUT:1]
resetn input
word_data_received input wire [word_bits-1:0] Bus Interface
word_send_data output [word_bits-1:0]
word_received input wire
PHASE_A1 input wire [`DUAL_HBRIDGE-1:0] Phase A
PHASE_A2 output wire [`DUAL_HBRIDGE-1:0] Phase A
PHASE_B1 output wire [`DUAL_HBRIDGE-1:0] Phase B
PHASE_B2 output wire [`DUAL_HBRIDGE-1:0] Phase B
VREF_A output wire [`DUAL_HBRIDGE-1:0] VRef
VREF_B output wire [`DUAL_HBRIDGE-1:0] VRef
CHARGEPUMP output wire
analog_cmp1 input wire [`ULTIBRIDGE-1:0]
analog_out1 output wire [`ULTIBRIDGE-1:0]
analog_cmp2 input wire [`ULTIBRIDGE-1:0]
analog_out2 output wire [`ULTIBRIDGE-1:0]
PHASE_A1 output wire [`ULTIBRIDGE-1:0] Phase A
PHASE_A2 output wire [`ULTIBRIDGE-1:0] Phase A
PHASE_B1 output wire [`ULTIBRIDGE-1:0] Phase B
PHASE_B2 output wire [`ULTIBRIDGE-1:0] Phase B
PHASE_A1_H output wire [`ULTIBRIDGE-1:0] Phase A
PHASE_A2_H output wire [`ULTIBRIDGE-1:0] Phase A
PHASE_B1_H output wire [`ULTIBRIDGE-1:0] Phase B
PHASE_B2_H output wire [`ULTIBRIDGE-1:0] Phase B
ENC_B output wire [num_encoders-1:0]
ENC_A input wire [num_encoders-1:0]
buffer_dtr output wire Event IO
move_done output wire
halt input wire
STEPINPUT input wire [num_motors-1:0]
DIRINPUT input wire [num_motors-1:0]
ENINPUT input wire [num_motors-1:0]
STEPOUTPUT input wire [num_motors-1:0]
DIROUTPUT output wire [num_motors-1:0]
ENOUTPUT output wire [num_motors-1:0]
CLK input
pwm_clock input

Signals

Name Type Description
j integer Iteration consts
status_reg_ro wire [word_bits-1:0] Status Register (read-only)
stepper_faultn wire [num_motors-1:0]
encoder_faultn wire [num_encoders-1:0]
encoder_count wire [encoder_bits-1:0]
encoder_velocity wire [encoder_velocity_bits-1:0]
encoder_velocity_counter wire [encoder_velocity_bits-1:0]
phase_angle wire [9:0]
config_reg_rw reg [word_bits-1:0]
enable_r wire [num_motors-1:0] Config Register - Set mappings for internal wiring
brake_r wire [num_motors-1:0]
clock_divisor wire [7:0]
microsteps reg [7:0]
current reg [current_bits-1:0]
config_offtime reg [9:0]
config_blanktime reg [7:0]
config_fastdecay_threshold reg [9:0]
config_minimum_on_time reg [7:0]
config_current_threshold reg [10:0]
config_invert_highside reg
config_invert_lowside reg
config_chargepump_period reg [7:0] one chargepump for all
telemetry_reg_ro reg [word_bits-1:0]
command_reg_rw reg [word_bits-1:0]
dir_r reg [num_motors:1]
increment_w wire [dda_bits-1:0] Per-axis DDA parameters
incrementincrement_w wire [dda_bits-1:0]
move_duration_w wire [move_duration_bits-1:0] DDA module input wires determined from buffer
capture_telemetry wire Any register/wire below this point is outside user space
writemoveind reg [MOVE_BUFFER_BITS:0] Move buffer
moveind wire [MOVE_BUFFER_BITS:0] set via DDA FSM
stepready reg [MOVE_BUFFER_SIZE:0]
dda_tick wire
dda_step wire [num_motors-1:0] Step IO
dir wire [num_motors-1:0]
step wire [num_motors-1:0]
enable wire [num_motors-1:0]
step_input_r wire [num_motors-1:0]
dir_input_r wire [num_motors-1:0]
en_input_r wire [num_motors-1:0]
dir wire [num_motors-1:0]
step wire [num_motors-1:0]
enable wire [num_motors-1:0]
step_encoder wire [encoder_bits-1:0] step encoder
loading_move wire
executing_move wire
message_word_count reg [$clog2(command_reg_end)-1:0] use_dda State Machine for handling SPI Messages
message_header reg [7:0]
awaiting_more_words wire check if the Header indicated multi-word transfer
word_received_rising wire
nmot reg [$clog2(num_motors):0]
dma_addr reg [7:0]

Constants

Name Type Value Description
CMD_COORDINATED_STEP 8'h01
CMD_STATUS_REG 8'hf1
CMD_CONFIG_REG 8'hf2
MOVE_BUFFER_SIZE BUFFER_SIZE - 1 This is the zero-indexed end index
MOVE_BUFFER_BITS $clog2(BUFFER_SIZE) - 1 number of bits to index given size
status_version 0 --- Status Register --- Status register offset aliases, These may be used in instantiated modules via dot access, e.g. rapcores.status_version for procedural interface generation
status_channel_info 1
status_encoder_fault 2
status_stepper_fault 3
status_encoder_position_start 4
status_encoder_position_end status_encoder_position_start + reserved_channels - 1
status_encoder_velocity_start status_stepper_fault + 1
status_encoder_velocity_end status_encoder_velocity_start + reserved_channels - 1
status_phase_angle_start status_encoder_velocity_end + 1
status_phase_angle_end status_phase_angle_start + reserved_channels - 1
status_reg_end status_phase_angle_end
config_enable 0 --- Config Register --- Config Register offset aliases
config_brake 1
config_clocks 2
config_reg_end config_clocks
telemetry_reg_end num_encoders*2 - 1 --- Telemetry Register --- Telemetry Register
command_reg_end (2 + num_motors * 2) --- Command Register --- Command Register

Processes

  • unnamed: ( @(posedge CLK) )

Type: always

  • unnamed: ( @(posedge CLK) )

Type: always

Instantiations

  • stepin_m: register_input
  • dirin_m: register_input
  • enin_m: register_input
  • cd0: clock_divider

Description
DDA Setup Clock divider used to continually make DDA ticks

  • word_recieved_edge_rising: rising_edge_detector






register_input

TerosHDL

Entity: register_input

  • File: register_input.v

Diagram

width clk [width-1:0] in [width-1:0] out

Generics

Generic name Type Value Description
width 1

Ports

Port name Direction Type Description
clk input
in input [width-1:0]
out output [width-1:0]

Processes

  • unnamed: ( @(posedge clk) )

Type: always







analog_out

TerosHDL

Entity: analog_out

  • File: analog_out.v

Diagram

wire clk wire resetn wire [7:0] pwm1 wire [7:0] pwm2 wire [10:0] current_threshold wire analog_out1 wire analog_out2

Description

SPDX-License-Identifier: ISC

Ports

Port name Direction Type Description
clk input wire
resetn input wire
pwm1 input wire [7:0]
pwm2 input wire [7:0]
analog_out1 output wire
analog_out2 output wire
current_threshold input wire [10:0]

Signals

Name Type Description
pwm_counter reg [10:0]

Processes

  • unnamed: ( @(posedge clk) )

Type: always







pwm_pll_ice40_140

TerosHDL

Entity: pwm_pll

  • File: pwm_pll_ice40_140.v

Diagram

clock_in clock_out locked

Description

*

Ports

Port name Direction Type Description
clock_in input
clock_out output
locked output

Instantiations

  • uut: SB_PLL40_CORE






pwm_pll_ecp5_200

TerosHDL

Entity: pwm_pll

  • File: pwm_pll_ecp5_200.v

Diagram

clock_in clock_out locked

Description

diamond 3.7 accepts this PLL diamond 3.8-3.9 is untested diamond 3.10 or higher is likely to abort with error about unable to use feedback signal cause of this could be from wrong CPHASE/FPHASE parameters

Ports

Port name Direction Type Description
clock_in input 27 MHz, 0 deg
clock_out output 199.8 MHz, 0 deg
locked output

Instantiations

  • pll_i: EHXPLLL






dda_fsm

TerosHDL

Entity: dda_fsm

  • File: dda_fsm.v

Diagram

buffer_bits buffer_size move_duration_bits clk resetn dda_tick [move_duration_bits-1:0] move_duration [buffer_size-1:0] stepready loading_move executing_move move_done finishedmove [buffer_bits-1:0] moveind buffer_dtr

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
buffer_bits 2
buffer_size 1
move_duration_bits 32

Ports

Port name Direction Type Description
clk input
resetn input
dda_tick input
move_duration input [move_duration_bits-1:0]
loading_move output
executing_move output
move_done output
finishedmove output
moveind output [buffer_bits-1:0]
stepready input [buffer_size-1:0]
buffer_dtr output

Signals

Name Type Description
stepfinished reg [buffer_size-1:0]
processing_move wire State managment
tickdowncount reg [move_duration_bits-1:0]
dda_tick_r reg [1:0]

Processes

  • unnamed: ( @(posedge clk) )

Type: always







spi_pll_ice40_64

TerosHDL

Entity: spi_pll

  • File: spi_pll_ice40_64.v

Diagram

clock_in clock_out locked

Description

*

Ports

Port name Direction Type Description
clock_in input
clock_out output
locked output

Instantiations

  • uut: SB_PLL40_CORE






pwm

TerosHDL

Entity: pwm

  • File: pwm.v

Diagram

bits resetable delayed clk resetn [bits-2:0] delay [bits-1:0] val pwm

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
bits 8
resetable 0
delayed 0

Ports

Port name Direction Type Description
clk input
resetn input
delay input [bits-2:0] delay should never be more than half the period
val input [bits-1:0]
pwm output

Signals

Name Type Description
accum reg [bits-1:0] FPGA ONLY






microstep_counter

TerosHDL

Entity: microstep_counter

  • File: microstep_counter.v

Diagram

[7:0] pos [5:0] cos_index1 [5:0] cos_index2 [3:0] sw

Description

SPDX-License-Identifier: ISC

Ports

Port name Direction Type Description
pos input [7:0]
cos_index1 output [5:0]
cos_index2 output [5:0]
sw output [3:0]






dual_hbridge

TerosHDL

Entity: dual_hbridge

  • File: dual_hbridge.v

Diagram

current_bits microstep_bits vref_off_brake microstep_count clk resetn pwm_clk enable brake [current_bits-1:0] current [phase_ct_end:0] phase_angle phase_a1 phase_a2 phase_b1 phase_b2 vref_a vref_b wire faultn

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
current_bits 4 bit precision of current
microstep_bits 8 bit precision of microsteps
vref_off_brake 1 "decay mode"
microstep_count 256 quarter-cycle divisions

Ports

Port name Direction Type Description
clk input
resetn input
pwm_clk input Clock for PWM
phase_a1 output Phase A
phase_a2 output Phase A
phase_b1 output Phase B
phase_b2 output Phase B
vref_a output vref - Phase A
vref_b output vref - Phase B
enable input
brake input
current input [current_bits-1:0]
phase_angle input [phase_ct_end:0] represents location in 0 -> 2pi electrical cycle
faultn output wire

Signals

Name Type Description
phase_polarity wire [1:0] TODO Coil Polarities and Decay modes could go into a "driver" layer once the SVM handles polarities well.------------------------------- Coil Polarities------------------------------- determine phase polarity from quadrant
brake_a wire ------------------------------- Decay Modes------------------------------- Set braking when PWM off (type of decay for integrated bridges without current chop)
brake_b wire ------------------------------- Decay Modes------------------------------- Set braking when PWM off (type of decay for integrated bridges without current chop)

Constants

Name Type Value Description
phase_ct_end $clog2(microstep_count*4) - 1 Compute the lower bits need from the step_count for the 0 -> 2pi phase count. Microsteps is quarter wave but we want a full electrical cycle

Instantiations

  • svm0: space_vector_modulator

Description
This is the integer value of the encoded SVM pulse N Phases are packed here, to be unpacked elsewhere wire [2*(current_bits+microstep_bits)-1:0] vref_val_packed;------------------------------- Space Vector Modulation-------------------------------







edge_detector

TerosHDL

dda_timer

TerosHDL

Entity: dda_timer

  • File: dda_timer.v

Diagram

dda_bits phase_angle_bits step_encoder_bits resetn signed [dda_bits-1:0] increment signed [dda_bits-1:0] incrementincrement loading_move executing_move dda_tick CLK signed [phase_angle_bits-1:0] phase_angle signed [step_encoder_bits-1:0] step_encoder wire [dda_bits-2:0] substep_accumulator

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
dda_bits 64
phase_angle_bits 10
step_encoder_bits 24

Ports

Port name Direction Type Description
resetn input
increment input signed [dda_bits-1:0]
incrementincrement input signed [dda_bits-1:0]
loading_move input
executing_move input
phase_angle output signed [phase_angle_bits-1:0]
step_encoder output signed [step_encoder_bits-1:0]
substep_accumulator output wire [dda_bits-2:0] this is the fractional part of our fixed-point
dda_tick input
CLK input

Signals

Name Type Description
accumulator reg signed [step_encoder_bits+dda_bits-2:0] This implements a fixed point scheme suitable for carry chain optimizations and allows for both implicit and explicit timing modes. We use one less bit than the dda_bits (fractional) element since increments are signed and we use the bottom bits of the integral portion for commutation and location encoding
increment_r reg signed [dda_bits-1:0]
dda_tick_rising wire Step Trigger condition

Processes

  • unnamed: ( @(posedge CLK) )

Type: always

Instantiations

  • dda_rising: rising_edge_detector






pwm_pll

TerosHDL

Entity: pwm_pll

  • File: pwm_pll.v

Diagram

wire clock_in wire clock_out wire locked

Description

SPDX-License-Identifier: ISC Dummy PLL module for sim

Ports

Port name Direction Type Description
clock_in input wire
clock_out output wire
locked output wire






mytimer_10

TerosHDL

Entity: mytimer_10

  • File: mytimer_10.v

Diagram

WIDTH clk resetn start_enable [WIDTH-1:0] start_time [WIDTH-1:0] timer done

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
WIDTH 10

Ports

Port name Direction Type Description
clk input
resetn input
start_enable input
start_time input [WIDTH-1:0]
timer output [WIDTH-1:0]
done output single cycle timer done event

Signals

Name Type Description
run reg
counter reg [WIDTH-1:0]

Processes

  • unnamed: ( @(posedge clk) )

Type: always







quad_enc

TerosHDL

Entity: quad_enc

  • File: quad_enc.v

Diagram

encbits enable_velocity velocity_bits wire resetn wire clk wire a wire b faultn [encbits-1:0] count [velocity_bits-1:0] velocity [velocity_bits-1:0] velocity_counter

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
encbits 64
enable_velocity 1
velocity_bits 32

Ports

Port name Direction Type Description
resetn input wire
clk input wire
a input wire
b input wire
faultn output
count output [encbits-1:0]
velocity output [velocity_bits-1:0]
velocity_counter output [velocity_bits-1:0]

Signals

Name Type Description
a_stable reg [2:0] Hold sample before compare for stability
b_stable reg [2:0] Hold sample before compare for stability
i_stable reg [2:0] Hold sample before compare for stability
step_a wire Step if a changed
step_b wire Step if b changed
step wire Step if a xor b stepped
direction wire Direction determined by comparing current sample to last

Processes

  • unnamed: ( @(posedge clk) )

Type: always







space_vector_modulator

TerosHDL

Entity: space_vector_modulator

  • File: space_vector_modulator.v

Diagram

current_bits microstep_bits phase_ct_bits center_aligned phases microsteps clk resetn pwm_clk [current_bits-1:0] current [phase_ct_bits-1:0] phase_ct [phases-1:0] vref_pwm

Description

SPDX-License-Identifier: ISC Space Vector Modulator (one, two and three Phase) https://en.wikipedia.org/wiki/Space_vector_modulation http://rapcores.org/rapcores/motor_control.html#space-vector-modulation We don't handle polarities here, all values are on/off timings. polarities and signedness is handled in the bridge controller.

Generics

Generic name Type Value Description
current_bits 4
microstep_bits 8
phase_ct_bits 8
center_aligned 1
phases 2
microsteps 64

Ports

Port name Direction Type Description
clk input
resetn input
pwm_clk input
vref_pwm output [phases-1:0]
current input [current_bits-1:0] also called Phase Vector amplitude
phase_ct input [phase_ct_bits-1:0] Represents 0 -> 2pi integer range

Signals

Name Type Description
phase_table reg [microstep_bits-1:0] Table of phase agnles (BRAM on FPGA)
i integer
phase reg [microstep_bits-1:0] sine value based on phase location (retrieved from BRAM)
pwm wire [microstep_bits+current_bits-1:0] sine value scaled by the current
pwm_delay wire [microstep_bits+current_bits-2:0] assign vref_val = {pwm[0], pwm[1]}; PWM Types: Center Aligned A: _
phase_idx wire [idx_end:0]

Constants

Name Type Value Description
can_delay center_aligned && phases > 1 center aligned delay only possible with phases > 1
phase_table_end integer microsteps*2-1 microsteps commonly means quarter-wave resolution however we store a half wave to get a true zero PWM crossing
pi real 3.1415926535897 Initialize sine table into BRAM
idx_end phase_ct_bits - 2

Processes

  • unnamed: ( @(posedge clk) )

Type: always







mytimer_8

TerosHDL

Entity: mytimer_8

  • File: mytimer_8.v

Diagram

WIDTH clk resetn start_enable [WIDTH-1:0] start_time [WIDTH-1:0] timer

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
WIDTH 8

Ports

Port name Direction Type Description
clk input
resetn input
start_enable input
start_time input [WIDTH-1:0]
timer output [WIDTH-1:0]

Signals

Name Type Description
counter reg [WIDTH-1:0]

Processes

  • unnamed: ( @(posedge clk) )

Type: always







mytimer

TerosHDL

Entity: mytimer

  • File: mytimer.v

Diagram

WIDTH clk resetn start_enable [WIDTH-1:0] start_time [WIDTH-1:0] timer done

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
WIDTH `DEFAULT_TIMER_WIDTH

Ports

Port name Direction Type Description
clk input
resetn input
start_enable input
start_time input [WIDTH-1:0]
timer output [WIDTH-1:0]
done output single cycle timer done event

Signals

Name Type Description
run reg
counter reg [WIDTH-1:0]

Processes

  • unnamed: ( @(posedge clk) )

Type: always







clock_divider

TerosHDL

Entity: clock_divider

  • File: clock_divider.v

Diagram

divider_bits resetn [divider_bits-1:0] divider clk tick

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
divider_bits 8

Ports

Port name Direction Type Description
resetn input
divider input [divider_bits-1:0]
tick output
clk input

Signals

Name Type Description
accum reg [divider_bits-1:0]

Processes

  • unnamed: ( @(posedge clk) )

Type: always







rapcore

TerosHDL

Entity: rapcore

  • File: rapcore.v

Diagram

num_motors move_duration_bits wire CS wire COPI wire [`ULTIBRIDGE-1:0] analog_cmp1 wire [`ULTIBRIDGE-1:0] analog_cmp2 wire [`QUAD_ENC-1:0] ENC_A wire BUFFER_DTR wire MOVE_DONE wire HALT wire [num_motors-1:0] STEPINPUT wire [num_motors-1:0] DIRINPUT wire [num_motors-1:0] ENINPUT wire [num_motors-1:0] STEPOUTPUT CLK wire [`LED:1] LED tinyfpgabx output wire SCK wire CIPO wire [`DUAL_HBRIDGE-1:0] PHASE_A1 wire [`DUAL_HBRIDGE-1:0] PHASE_A2 wire [`DUAL_HBRIDGE-1:0] PHASE_B1 wire [`DUAL_HBRIDGE-1:0] PHASE_B2 wire [`DUAL_HBRIDGE-1:0] VREF_A wire [`DUAL_HBRIDGE-1:0] VREF_B wire CHARGEPUMP wire [`ULTIBRIDGE-1:0] analog_out1 wire [`ULTIBRIDGE-1:0] analog_out2 wire [`ULTIBRIDGE-1:0] PHASE_A1 wire [`ULTIBRIDGE-1:0] PHASE_A2 wire [`ULTIBRIDGE-1:0] PHASE_B1 wire [`ULTIBRIDGE-1:0] PHASE_B2 wire [`ULTIBRIDGE-1:0] PHASE_A1_H wire [`ULTIBRIDGE-1:0] PHASE_A2_H wire [`ULTIBRIDGE-1:0] PHASE_B1_H wire [`ULTIBRIDGE-1:0] PHASE_B2_H wire [`QUAD_ENC-1:0] ENC_B wire [num_motors-1:0] ENOUTPUT wire [num_motors-1:0] DIROUTPUT wire [`LA_IN:1] LA_IN wire [`LA_OUT:1] LA_OUT RESETN resetn_in

Description

SPDX-License-Identifier: ISC

Generics

Generic name Type Value Description
num_motors `MOTOR_COUNT
move_duration_bits `MOVE_DURATION_BITS

Ports

Port name Direction Type Description
LED output wire [`LED:1]
output output tinyfpgabx
SCK output wire
CS input wire
COPI input wire
CIPO output wire
PHASE_A1 output wire [`DUAL_HBRIDGE-1:0] Phase A
PHASE_A2 output wire [`DUAL_HBRIDGE-1:0] Phase A
PHASE_B1 output wire [`DUAL_HBRIDGE-1:0] Phase B
PHASE_B2 output wire [`DUAL_HBRIDGE-1:0] Phase B
VREF_A output wire [`DUAL_HBRIDGE-1:0] VRef
VREF_B output wire [`DUAL_HBRIDGE-1:0] VRef
CHARGEPUMP output wire
analog_cmp1 input wire [`ULTIBRIDGE-1:0]
analog_out1 output wire [`ULTIBRIDGE-1:0]
analog_cmp2 input wire [`ULTIBRIDGE-1:0]
analog_out2 output wire [`ULTIBRIDGE-1:0]
PHASE_A1 output wire [`ULTIBRIDGE-1:0] Phase A
PHASE_A2 output wire [`ULTIBRIDGE-1:0] Phase A
PHASE_B1 output wire [`ULTIBRIDGE-1:0] Phase B
PHASE_B2 output wire [`ULTIBRIDGE-1:0] Phase B
PHASE_A1_H output wire [`ULTIBRIDGE-1:0] Phase A
PHASE_A2_H output wire [`ULTIBRIDGE-1:0] Phase A
PHASE_B1_H output wire [`ULTIBRIDGE-1:0] Phase B
PHASE_B2_H output wire [`ULTIBRIDGE-1:0] Phase B
ENC_B output wire [`QUAD_ENC-1:0]
ENC_A input wire [`QUAD_ENC-1:0]
BUFFER_DTR input wire
MOVE_DONE input wire
HALT input wire
STEPINPUT input wire [num_motors-1:0]
DIRINPUT input wire [num_motors-1:0]
ENINPUT input wire [num_motors-1:0]
STEPOUTPUT input wire [num_motors-1:0]
ENOUTPUT output wire [num_motors-1:0]
DIROUTPUT output wire [num_motors-1:0]
LA_IN output wire [`LA_IN:1]
LA_OUT output wire [`LA_OUT:1]
resetn_in output RESETN
CLK input

Signals

Name Type Description
BUFFER_DTR wire
MOVE_DONE wire
HALT wire
buffered_clk wire
buffered_clk wire
pwm_clock wire PLL for SPI Bus
pwmpll_locked wire
pwm_clock wire
spi_clock wire
spipll_locked wire
spi_clock wire
resetn wire Reset
resetn_counter reg [7:0]
resetn_counter reg [7:0] FPGA ONLY
reset wire
word_send_data wire [63:0] Word handler The system operates on 64 bit little endian words This should make it easier to send 64 bit chunks from the host controller
word_data_received wire [63:0]
word_received wire

Constants

Name Type Value Description
num_encoders `QUAD_ENC
num_encoders 0

Processes

  • unnamed: ( @(posedge buffered_clk) )

Type: always

  • unnamed: ( @(posedge buffered_clk) )

Type: always

Instantiations

  • ppll: pwm_pll
  • ppll: pwm_pll

Description
We only get buffered_clk here since it is primary/requisite PLL

  • ppll: spi_pll
  • word_proc: SPIWord






cosine

TerosHDL

Entity: cosine

  • File: cosine.v

Diagram

wire clk wire [5:0] cos_index wire [7:0] cos_value

Description

SPDX-License-Identifier: ISC

Ports

Port name Direction Type Description
clk input wire
cos_index input wire [5:0]
cos_value output wire [7:0]

Signals

Name Type Description
cos_r reg [7:0]

Processes

  • unnamed: ( @(posedge clk) )

Type: always







pwm_pll_ecp5_150

TerosHDL

Entity: pwm_pll

  • File: pwm_pll_ecp5_150.v

Diagram

clock_in clock_out locked

Description

diamond 3.7 accepts this PLL diamond 3.8-3.9 is untested diamond 3.10 or higher is likely to abort with error about unable to use feedback signal cause of this could be from wrong CPHASE/FPHASE parameters

Ports

Port name Direction Type Description
clock_in input 25 MHz, 0 deg
clock_out output 150 MHz, 0 deg
locked output

Instantiations

  • pll_i: EHXPLLL






spi_pll_ecp5_64

TerosHDL

Entity: spi_pll

  • File: spi_pll_ecp5_64.v

Diagram

clock_in clock_out locked

Description

diamond 3.7 accepts this PLL diamond 3.8-3.9 is untested diamond 3.10 or higher is likely to abort with error about unable to use feedback signal cause of this could be from wrong CPHASE/FPHASE parameters

Ports

Port name Direction Type Description
clock_in input 27 MHz, 0 deg
clock_out output 64.125 MHz, 0 deg
locked output

Instantiations

  • pll_i: EHXPLLL