SPI Specification

Definitions

• SPI Transfer: An 8 bit, Mode 0 MSB SPI communication

• Words: 64 bits of 8 little endian SPI transfers

• Message: A complete SPI transmission consisting of one or more words

• Forward Channel: SPI communication initiated by firmware to FPGA

• Reverse Channel: Data transmitted by FPGA to firmware during message transfer

• Motor Channel:

Versioning

RAPcores follows Semantic Versioning. This is still a pre-1.0 project so breaking changes are likely to happen with the SPI protocol. This document serves as the “as-built” reference for the RAPcores, and may deviate from documents outside this repository.

Overview

The SPI bus protocol is designed to allow for DMA with status/config registers and fused telemetry/command registers. The protocol is a thin wrapper over the register maps:

Header	Action	Transmission Length (Words)
0x01	Command/Telemetry Transfer	2 + 2*N motors
0xf1	Status Register	2
0xf2	Configuration Register	2

The SPI bus operated in peripheral mode 0 MSB.The protocol assumes any complete transfer is a 64 bit word. The word construction is set to little endian for improved compatibility with SPI controller devices.

Status/Config Commands - (0xf1 0xf2)

Coordinated Step Timer - 0x01

This message type specifies a move segment to be clocked out of the core. It uses 64bit words to specify the DDA values, and returns 32bit precision encoder readings.

I/O	Word 1 (Control / Status)								Words 2,4,6,etc.								Words 3,5,7,etc.
	B1	B2	B3	B4	B5	B6	B7	B8	B1	B2	B3	B4	B5	B6	B7	B8	B1	B2	B3	B4	B5	B6	B7	B8
CO	0x01	RESERVED	0bPONM_LKJI	0bHGFE_DCBA	dda_ticks				substep_increment_N								substep_increment_increment_N
CI	Status word is TBD												shaft_encoder_N								effector_encoder_N

Notes

• CO is the forward SPI channel from the controller to the peripheral (core). CI is the reverse channel.

• Word1 is the 64bit message header, consisting of 8 bytes, MSbyte = B1, LSbyte = B8

• Word1 from CO is the control word. Word1 back from the CI is the status word

• __N_ is the number of motor channels configured - making the message length 2xN+1 64bit words

• CO Word1, Byte1 is the message number in the control word

• CO direction bitfield: bit A is direction for motor 0; bit P is direction for motor 15;

• Direction is arbitrary - 0 is considered Normal, 1 is Reverse

• CO dda_ticks is the segment length in DDA ticks. For example, a value of 16000 at a 16 MHz DDA clock sets a 1 mS segment

• CI shaft_encoder_N is the signed 32-bit absolute, unscaled encoder count for the shaft encoder. If no encoder is present it’s absolute step count.

• CI effector_encoder_N is the signed 32-bit absolute, unscaled encoder count for the effector encoder; or zero if no encoder present